The present invention relates to a semiconductor memory device and method of controlling an operation thereof and specifically, to a flash memory device and method for controlling a pre-program operation.
In general, a flash memory device is operable in a read operation, a program operation, and an erase operation. The erase operation is accomplished with Fowler-Nordheim tunneling effect induced at an insulation film between a P-well and a floating gate of a memory cell. By the erase operation, data stored in all memory cells in a memory cell block are erased at a time. The erase operation is carried out in the unit of memory cell block. There would be memory cells that have been already erased (i.e., memory cells programmed with data ‘0’). As the pre-erased memory cells have low threshold voltages, it would produce over-erasure when the erase operation is resumed (i.e., the threshold voltages are lowered too much). Therefore, in purpose of preventing such a result, the procedure of erasing the flash memory device includes a pre-program operation to adjust the threshold voltages of the whole memory cells on a first predetermined voltage level by preliminarily programming the whole memory cells before the erase operation. Meanwhile, the erasing speed of the memory cells included in the flash memory device may vary in accordance with manufacturing process conditions. In other words, there would be memory cells with faster erasing speed and memory cells with slower erasing speed. Thus, if an erasing time is established to the memory cells with the slower erasing speed, the memory cells with the faster erasing speed may be over-erased. In order to prevent such a result, the erasing procedure includes a post-program operation to adjust the threshold voltages of the whole memory cells on a second predetermined voltage levels by conducting a program operation for the whole memory cells for a predetermined time after the erase operation.
FIG. 1 is a circuit diagram illustrating memory cell blocks and bitline selection circuits, explaining a pre-program operation in a conventional flash memory device. Referring to FIG. 1, there are disclosed memory cell blocks MR1˜MRN (N is an integer) and the bitline selection circuit 10. For simplification of the drawing, there are just disclosed memory cells that are connected to a pair of bitlines BLe and BLo, among memory cells included in each of the memory cell blocks MR1˜MRN. For example, while executing the pre-program operation for the memory cell block MR1, a power source voltage VCC is applied to a drain selection line DSL and a ground voltage 0V is applied to a source selection line SSL. As a result, a drain selection transistor DST of the memory cell block MR1 is turned on while a source selection transistor SST is turned off. A high voltage HVP (e.g., 15˜20V) is applied to wordlines WL0˜WLM (M is an integer). Thus, memory cells C0˜CM of the memory cell block MR1 are turned on. And, the power source voltage VCC is applied to a common source line CSL and NMOS transistors N1 and N2 of the bitline selection circuit 10 are turned on to apply a signal VIRPWR to the bitlines BLe and BLo. During this, the signal VIRPWR has a voltage level of 0 and NMOS transistors N3 and N4 of the bitline selection circuit 10 are turned off in response to selection signals BSLe and BSLo. As a result, a great voltage gap is generated between drains and gates of the memory cells C0˜CM (M is an integer), which causes injection of electrons to floating gates of the memory cells C0˜CM to conduct the pre-program operation.
As aforementioned, the memory cells C0˜CM are pre-programmed by the voltage of 0V applied to the bitlines BLo and BLe. Meanwhile, as the bitlines BLe and BLo are shared by all the memory cell blocks MR1˜MRN, they have very large loading capacitance. Thus, it increases the time for sufficiently discharging the bitlines BLo and BLe to 0V in response to the signal VIRPWR, increasing the amount of current consumption. Further, the parasitic capacitance, under the bitlines BLe and BLo, caused by the high voltage HVP applied to the wordlines WL0˜WLM acts to further increase the discharging time and current consumption. Therefore, in the pre-program operation in the conventional flash memory device, the discharging time of the bitlines BLe and BLo increases to make the whole erasing time longer and current consumption larger.